EDN

How to design an FPGA architecture tailored for efficiency and performance

Until relatively recently, the majority of FPGA architectures were developed using 4-input lookup tables (LUTs), where each LUT is constructed from SRAM bits storing digital (0 or 1) information. Also ...
Design-Reuse

Synthesizable Switching Logic For Network-On-Chip Designs on 90nm Technologies

Study on synthesizable switch structures for network-on-chip designs is presented. Sum-of-products one-hot multiplexing is identified as an appealing general-purpose choice with a low latency and an ...
EDN

FPGA vendors revise logic for sub-100-nm era

San Jose, Calif. – As the 90-nanometer technology node kicks in, chip vendors are finding they must abandon some time-tested principles to navigate the transition. Case in point: Xilinx Inc. and ...