EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
EDN

Magma creates structured ASIC flow for ChipX

SAN JOSE, Calif. — Magma Design Automation Inc. and structured ASIC vendor ChipX Corp. have put together a unified RTL-to-GDSII design flow based on Magma's Blast Create and Blast Fusion for designers ...
Electronics Weekly

Following the road from ASIC to FPGA

We are seeing a growing number of engineering teams transitioning from ASIC into FPGA design teams. Many of these teams would like to leverage the tools, flows, and methodologies they’ve previously ...
Design-Reuse

Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms

Magma design flow supports ChipX CX5000 and future structured ASIC architectures SANTA CLARA, Calif., September 14, 2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design ...
Electronic Design

Flow Software Cuts ASIC Modelling Time

It is important to model an SoC well in advance to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run. It ...
Semiconductor Engineering

SpyGlass Application In An FPGA To ASIC Conversion Flow

Mapping from a field programmable gate array (FPGA) to an application specific IC (ASIC) is subject to some limitations. This white paper identifies some of the most common limitations in this mapping ...
Design-Reuse

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...