Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
EDN

Aldec simulator links to Simulink

SAN JOSE, Calif. — ASIC and FPGA verification tool vendor Aldec Inc. has added a cosimulation wizard to its Active-HDL simulation environment to connect the environment to Mathworks' Simulink. The new ...
Electronic Design

Graphical Code Coverage Tool Speeds Design Debugging

Code Snooper, a code coverage software tool for use with the Active-HDL design and verification environment is integrated with the Active-HDL simulation kernel and does not require additional ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...
EDN

FPGA toolset adds C synthesis interface

SANTA CRUZ, Calif. Bringing C language synthesis to FPGA design, Aldec on Wednesday (May 21) rolled out its Active-HDL version 6.1 toolset offering an interface to Celoxica's DK2 Design Suite. The ...