This is going to be a column that’s divided into three sections. It’s based on a question that a student posed in the EEWeb forums, and he also sent it directly to yours truly. The core of this ...

As I mentioned in my recent columns on the topic of adding pull-up or pull-down resistors to the inputs of unused or partially used logic gates and functions (see Part 1, Part 2, and Part 3), I was ...

If you’d like to squeeze more functionality into less space, while simplifying inventory and reducing system cost, then check out NXP’s configurable and combination logic. These flexible and ...

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...