EDN

Multiple clock domain SoCs: Addressing structural defects

In the previous blog (Synchronization techniques for multi-clock domain SoCs& FPGAs), we studied different types of synchronization techniques to synchronize signals from one clock domain to another.
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
EDN

Timing Diagram Editors Simplify FPGA Synthesis

SynaptiCAD has released an updated version of its timing diagram editor family that simplifies creating the Synopsys Design Constraint (SDC) files used to define the ...
Design-Reuse

Low Power High Density Clock Gate

This paper presents a low power Clock Gating scheme for clock power improvement that reduces power dissipation by deactivating the clock signal to an inactive value (for clock gating cell) when clock ...
Design-Reuse

Clock Domain Crossing Glitch Detection Using Formal Verification

Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With the integration of multiple designs, various clock domains are ...
Electronic Design

Bulletproof Your System Timing With Programmable Clocks

Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if ...