The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

Have you ever designed a product that you thought was ready to ship only to have it fail testing by not meeting safety requirements? Months can be lost and mistakes repeated if a company doesn’t have ...

Connected devices and systems have become an integral part of our everyday life and we take this for granted. Finding the fastest way to our destination with a smartphone, reading the news on a tablet ...

Identify sources of unnecessary cognitive load and apply strategies to focus on meaningful analysis and exploration.

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of ...