Semiconductor Engineering

3D DRAM with CBA Technology (Georgia Tech)

Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures,” was published by researchers at Georgia Tech. Abstract “3D DRAM has emerged as a promising ...
EDN

Under the Hood: New DRAM chip gets due notice

Over the years, there have not been many drastic changes to the structure of DRAM devices. There have been a few tweaks here and there to account for smaller process geometries and to optimize design, ...
sciencex

Imec Demonstrates Capacitor-less IGZO-Based DRAM Cell With >400s Retention Time

This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access ...
EDN

Speed with flexible design critical to embedded DRAM for SoCs

Steven Tomashot, Senior Technical Staff Member, IBM Microelectronics Division, Essex Junction, Vermont, Subramanian S. Iyer, Manager, System Scale Integration, IBM Microelectronics Division, Hopewell ...
Electronic Design

Overcome Traditional Memory-Speed Barriers With Embedded DRAM

For applications where performance is of primary importance, designers have traditionally chosen SRAM technology over DRAM. Although commodity DRAM offers much higher density and a lower cost per bit, ...
Semiconductor Engineering

Virtual Exploration Of Novel Vertical DRAM Architectures

Process and device technologies have had to overcome numerous technical challenges as DRAM memory devices have transitioned between different cell architectures. When DRAM technology nodes went beyond ...
Electronic Design

Solving DRAM’s Row Hammer Problem Using Vertical Epitaxial Transistors

What is DRAM’s row hammer problem and why is it important? How vertical epitaxial transistors solve the problem. How Spin Memory’s Universal Selector works. How the Universal Selector can improve DRAM ...