Nasdaq

Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development

Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP. Integrated and optimized solutions will focus on ...

Milk-V Titan gives developers a plug-and-play RISC-V desktop

Unlike previous prototypes, which were limited to embedded or experimental use, the Titan targets mainstream usability. Its ...
Geeky Gadgets

RISC OS alternative operating system hits Kickstarter

A new Kickstarter project has launched this month, looking for backers to help build a power saving computer operating system and push RISC OS to more hardware platforms. German developer Stefan ...
Semiconductor Engineering

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)

A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by researchers at Inha University, Intel Labs, Electronics and ...

Bolt wants to take on Nvidia by building a RISC-V graphics processor

Bolt Graphics wants to take on Nvidia and AMD by building a RISC-V graphics processor ...
The Next Platform

Strong Showing for First Experimental RISC-V Supercomputer

A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates a potential ...
Electronic Design

Adding Soft-Core RISC-V to FPGAs Improves Programmability

Advantages of using a soft-core RISC-V processor. The type of performance you can expect from using a soft-core RISC-V processor on the Speedster 7t. A full list of configurable features available on ...
Semiconductor Engineering

Manage Your Risk In RISC-V

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the ...
TechNode

China’s chip industry is embracing RISC-V

Every Wednesday and Friday, TechNode’s Briefing newsletter delivers a roundup of the most important news in China tech, straight to your inbox. Sign up On June 21, Nuclei System Technology, a Shanghai ...
Fox2Now St. Louis

Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Complete range of tests for the entire RISC-V core verification stack from ISA to system-level interaction and performance Test Suite Synthesis AI Technology tracks complex, un-predictable bugs and ...
TechSpot

Qualcomm announces RISC-V chip for Wear OS-based wearable devices

Highly anticipated: After betting on the future of RISC-V with an industry-wide alliance, Qualcomm is now bringing its first chip based on the open-source architecture to the mass market. The American ...
Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...