Despite its standardization as IEEE 1149.1 in 1990 and wide use in the industry, many test engineers and developers still do not fully understand the benefits of boundary scan test. The misconceptions ...

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often write about various aspects of digital IC test. If you started following the Test Voices blog when it was part of Test & ...

At Alcatel-Lucent, we test chassis-level products that provide 42 board slots on a midplane, essentially a passive backplane that accepts boards on its front and rear sides. Thirty-four of those slots ...

Bus-based packetized scan data decouples test delivery and core-level DFT requirements so core-level compression configuration can be defined completely independently of chip I/O limitations. Grouping ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...