Design-Reuse

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
Semiconductor Engineering

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores

This new technical paper titled “RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs” was published by researchers at University ...