EDN

Design of Standard Cell Library [Cadence ICFB, Synopsys DC, 0.5μmCMOS]

The Standard Cell Library consisting of basic gates with different inputs and drive strengths is designed in Cadence ICFB. This means creating layout, cmos_sch and symbol, behavioral, extracted, ...
EDN

Design-specific standard cells yield custom performance

A key limiting factor in standard cell based IC design is the standard cell library itself. This is because standard cell libraries don't offer the necessary variety of cells — in terms of ...
Semiconductor Engineering

Cell Library Verification Using Symbolic Simulation

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...
Business Wire

SilTerra Leverages Silvaco's Library Characterization and Optimization Tools to Boost Efficiency in the Development of its Foundry Standard Cell IPs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Silvaco Group, Inc. (“Silvaco”), a provider of TCAD, EDA software, and design IP, today announced that SilTerra has successfully deployed its library ...
Semiconductor Engineering

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)

A new technical paper titled “Novel Transformer Model Based Clustering Method for Standard Cell Design Automation” was published by researchers at Nvidia. “Standard cells are essential components of ...
Design-Reuse

Standard Cell Library in SkyWater 90nm

This Standard Cell Library in SkyWater 90nm (S90 / C9) CMOS process is a low-leakage digital standard cell library that targets power-efficient and lo ...