The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...

In its continuing efforts to harness the considerable verification power of SystemVerilog, Synopsys has rolled out extensions to the verification methodology spelled out in its System Verilog ...

Hardware for integer or fixed-point arithmetic is relatively simple to design, at least at the register-transfer level. If the range of values and precision that can be represented with these formats ...

The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...

The iterations a specification goes through in a given project. Are chip design and verification specs, and hardware and software specs, separate entities? Automation of the specification process.