For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...

SAN JOSE, CA--(Marketwire -09/04/12)- EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have ...

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...

UVM (Universal Verification Methodology) is widely used in creating object-oriented test environments. UVM provides two key benefits to verification engineers; one is reusability; the other is ...

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal ...

What's all the buzz on UVM? The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology (UVM) ...