As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the ...

In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...

The past decade or so has seen some really phenomenal capacity growth and similarly remarkable software technology in support of distributed-memory systems. When work can be spread out across a lot of ...

A fundamentally new approach to cache coherence has been released -- the first in more than three decades. Whereas with existing techniques, the directory's memory allotment increases in direct ...

Managing a cache so that data are not lost or overwritten. For example, when data are updated in a cache but not yet transferred to the target memory or disk, the chance of corruption is greater.

In today’s digital economy, high-scale applications must perform flawlessly, even during peak demand periods. With modern caching strategies, organizations can deliver high-speed experiences at scale.

Mentor Graphics Questa and Veloce Verification Platforms Add Cache Coherency and Interconnect Performance for ARM AMBA 5 CHI and AMBA 4 ACE Designs "Many teams in multi-core SoC design are moving to ...

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems ...

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...

Part 1: A look at the impact of communication across multiple processors on an SoC and how to to make that more efficient. Managing how the processors in an SoC talk to one another is no small feat, ...